Memory system and operating method thereof

ABSTRACT

A memory system includes a memory device including a plurality of command registers; and a memory controller configured to determine whether an empty command register exists among the plurality of command registers, and transmit a new command to the memory device, when an empty command register exists, wherein, when the new command is transmitted from the memory controller, the memory device stores the transmitted new command in the empty command register.

CROSS-REFERENCES TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 15/387,873 filed on Dec. 22, 2016, which claims benefits of priority of Korean Patent Application No. 10-2016-0091120 filed on Jul. 19, 2016. The disclosure of each of the foregoing application is incorporated herein by reference in its entirety.

BACKGROUND 1. Technical Field

Various embodiments generally relate to a semiconductor device, and, more particularly, to a memory system and an operating method thereof.

2. Related Art

A semiconductor memory device is a memory device which is realized using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs) and indium phosphide (InP). A semiconductor memory device is generally classified into a volatile memory device and a nonvolatile memory device.

A volatile memory device is a memory device which loses stored data when power supply is interrupted. Examples of a volatile memory device include an SRAM (static RAM), a DRAM (dynamic RAM) and an SDRAM (synchronous DRAM). A nonvolatile memory device is a memory device which retains stored data even when power supply is interrupted. A nonvolatile memory device includes a ROM (read only memory), a PROM (programmable ROM), an EPROM (electrically programmable ROM), an EEPROM (electrically erasable and programmable ROM), a flash memory, a PRAM (phase change RAM), an MRAM (magnetic RAM), an RRAM (resistive RAM), and an FRAM (ferroelectric RAM). A flash memory is generally classified into a NOR flash and a NAND flash.

SUMMARY

Various embodiments are directed to a memory system having a simplified interface between a controller and a memory device, and an operating method thereof. The memory system may significantly improve the performance of the memory device.

In an embodiment, a memory system may include: a memory device including a plurality of command registers; and a memory controller configured to determine whether an empty command register exists among the plurality of command registers, and transmit a new command to the memory device, when an empty command register exists, wherein, when the new command is transmitted from the memory controller, the memory device stores the transmitted new command in the empty command register.

In an embodiment, a memory system may include: a memory device; and a memory controller configured to control an operation of the memory device, the memory device including: plural command registers configured to store commands transmitted from the memory controller; a command state register configured to store state informations of the commands stored in the command registers; and a control logic configured to store the transmitted command in an empty one of the command registers, wherein the memory controller determines by checking the command state register whether an empty command register exists among the command registers, and transmits a new command to the memory device when the empty command register exists.

In an embodiment, a method for operating a memory system including a memory device which includes a plurality of command registers and a memory controller which controls an operation of the memory device may include: determining whether an empty command register exists among the plurality of command registers; transmitting a new command to the memory device, when an empty command register exists; and storing the transmitted command in the empty command register.

In an embodiment, a memory system may include: a memory device including a plurality of command registers for storing provided commands, and suitable for executing the stored commands; and a memory controller suitable for controlling the memory device by providing the commands to the memory device, wherein a memory controller provides a new command to the memory device when one or more among the stored commands are execution-completed, and wherein the memory device stores the new command in one among the command registers corresponding to the execution-completed commands.

The memory device further includes a command state register for storing execution statuses of the stored commands, and the memory device updates the execution statuses at least when one or more of the stored commands are execution-completed.

The memory controller determine whether to provide the new command according to the execution statuses.

The memory device executes the stored command in order of priority.

The memory device suspends a command in the process of being executed and having a lower priority, and executes another command having a higher priority, among the stored commands.

In an embodiment, a method for operating a memory system including a memory device and a memory controller may include: providing, by the memory controller, commands to the memory device; storing, by the memory device, the provided commands in command registers of the memory device; and executing, by the memory device, the stored commands, wherein a new command is provided to the memory device when one or more among the stored commands are execution-completed, and wherein the new command is stored in one among the command registers corresponding to the execution-completed commands.

The method further include: storing execution statuses of the stored commands; and updating the execution statuses at least when one or more of the stored commands are execution-completed.

The providing of the commands includes determining, by the memory controller, whether to provide the new command according to the execution statuses.

The stored commands are executed in order of priority.

The executing of the stored commands includes suspending, by the memory device, a command in the process of being executed and having a lower priority among the stored commands, and executing, by the memory device, another command having a higher priority among the stored commands.

According to the embodiments, two commands may be stored in a memory device, and thus when execution of a first command is completed, a second command may be executed immediately. Accordingly, a memory controller does not need to transmit a separate cache command to the memory device, and thus the number of commands may be decreased thereby simplifying an interface.

According to the embodiments, even when it is in a busy state, the memory device may receive a command thereby shortening a command reception interval, and thus the performance of a memory system may be improved.

According to the embodiments, the memory device may suspend and resume execution of a command by itself, and thus the memory controller does not need to transmit a separate suspend/resume command to the memory device thereby reducing the number of command transmissions.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent to those skilled in the art to which the present invention belongs by describing in detail various embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram illustrating a memory system, in accordance with an embodiment of the present invention.

FIGS. 2A and 2B are diagrams illustrating representations of examples of command state registers, in accordance with embodiments of the present invention.

FIGS. 3A to 3D are representations of examples of diagrams to assist in the explanation of operations for a memory device of FIG. 1.

FIG. 4 is a block diagram illustrating a memory system, in accordance with another embodiment of the present invention.

FIG. 5 is a diagram illustrating register values for suspending conditions, in accordance with an embodiment of the present invention.

FIG. 6 is a flow chart of a method for operating a memory system, in accordance with an embodiment of the present invention.

FIG. 7 is a flow chart of a method for performing a suspending operation of a memory device, in accordance with an embodiment of the present invention.

FIG. 8 is a flow chart of a method for performing a suspending operation of a memory device, in accordance with another embodiment of the present invention.

FIG. 9 is a block diagram illustrating a data processing system including a memory system, in accordance with an embodiment of the present invention.

FIG. 10 is a block diagram illustrating a data processing system including a solid state drive (SSD), in accordance with an embodiment of the present invention.

FIG. 11 is a block diagram illustrating the SSD controller of the SSD of FIG. 10.

DETAILED DESCRIPTION

Hereinafter, a memory system and an operating method thereof will be described below with reference to the accompanying drawings through various examples of embodiments.

The present disclosure, however, may be embodied in various different forms, and should not be construed as being limited to the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the various aspects and features of the present invention to those skilled in the art.

It will be understood that, although the terms “first”, “second”, “third”, and so on may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element described below could also be termed as a second or third element without departing from the spirit and scope of the present invention.

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to more clearly illustrate the various elements of the embodiments. For example, in the drawings, the size of elements and the intervals between elements may be exaggerated compared to actual sizes and intervals for convenience of illustration.

It will be further understood that when an element is referred to as being “connected to”, or “coupled to” another element, it may be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or one or more intervening elements may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and “including” when used in this specification, specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs in view of the present disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well-known process structures and/or processes have not been described in detail in order not to unnecessarily obscure the present invention.

It is also noted, that in some instances, as would be apparent to those skilled in the relevant art, an element (also referred to as a feature) described in connection with one embodiment may be used singly or in combination with other elements of another embodiment, unless specifically indicated otherwise.

Hereinafter, the various embodiments of the present invention will be described in detail with reference to the attached drawings.

Referring now to FIG. 1 a memory system 10 is provided, in accordance with an embodiment of the present invention. T the memory system 10 may include a memory device 100 and a memory controller 200.

The memory system 10 may store data which may be accessed by a host device. The host device may be a portable electronic device such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, or a non-portable electronic device such as, a game player, a TV, an in-vehicle infotainment system.

The memory system 10 may be manufactured as any one of various storage devices according to the protocol of an interface which is electrically coupled with the host device. For example, the memory system 10 may be configured as at least one of various storage devices such as a solid state drive, a multimedia card in the form of an MMC, an eMMC, an RS-MMC and a micro-MMC, a secure digital card in the form of an SD, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, a memory stick, and the like.

The memory system 10 may be manufactured as any one among various package types such as a package-on-package (PoP), a system-in-package (SIP), a system-on-chip (SoC), a mufti-chip package (MCP), a chip-on-board (CoB), a wafer-level fabricated package (WFP) and a wafer-level stack package (WSP) and the like.

The memory device 100 may operate as the storage medium of the memory system 10. The memory device 100 may be configured by at least one of various nonvolatile memory devices such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase change random access memory (PRAM) using a chalcogenide alloy, a resistive random access memory (RERAM) using a transition metal compound, according to memory cells, and the like.

The memory device 100 may include a memory cell array 110, a control logic 120, a first command register 130, a second command register 140, a row decoder 150, a column decoder 160, a first page buffer 170, a second page buffer 180, and a command state register 190 operatively coupled through at least one internal bus.

The memory cell array 110 may include a plurality of memory cells (not shown). The memory cells may be respectively disposed at regions where a plurality of bit lines (not shown) and a plurality of word lines (not shown) intersect with each other. A memory cell may be a single level cell (SLC) storing one bit, or a multi-level cell (MLC) capable of storing 2-bit data, 3-bit data (a triple level cell (TLC)), or 4-bit data (a quad level cell (QLC)). The memory cell array 110 may include a plurality of memory cells selected from the group consisting of single level cells, 2-bit level cells, triple level cells, and quad level cells. In an embodiment, the memory cells may be hybrid cells, i.e., a combination of at least two of single level cells, 2-bit level cells, triple level cells, and quad level cells. In an embodiment, the memory cell array 110 may include memory cells arranged in a 2-dimensional horizontal structure. In yet another embodiment the memory cell array 110 may include memory cells arranged in a 3-dimensional vertical structure. Such structures are well known in the art and therefore we will not describe them any further for the sake of not obfuscating the description of the present invention with unnecessary well known details.

The control logic 120 may control one or more operations of the memory device 100 including write, read and erase operations of the memory device 100. For example, the control logic 120 may control a write operation and a read operation to be performed in the memory cell array 110, in response to a write command and a read command, respectively. The write and read commands may be transmitted to the memory device 100 from the memory controller 200. The write and read commands may be generated by the memory controller 200 in response to respective write and read requests received from a host (not shown) operatively coupled to the memory system 100. Also, the control logic 120 may control an erase operation to be performed in the memory cell array 110, in response to an erase command transmitted from the memory controller 200. As an example, a write operation and a read operation may be performed by the unit of a page, whereas an erase operation may be performed by the unit of a block. The memory cell array 110 may include a plurality of blocks, and each block may include a plurality of pages.

The control logic 120 may transmit a row address ADDR_row for selecting a word line and a column address ADDR_col for selecting a bit line, to the row decoder 150 and the column decoder 160, respectively, based on an address provided from the memory controller 200.

Each of the first and second command registers 130 and 140 may store a command transmitted from the memory controller 200. The commands stored in the first and second command registers 130 and 140 may be fetched and executed by the control logic 120 in a sequence in which the commands are transmitted from the memory controller 200.

The row decoder 150 may select any one among a plurality of word lines coupled with the memory cell array 110. For example, the row decoder 150 may receive the row address ADDR_row from the control logic 120. The row decoder 150 may select any one word line corresponding to the received row address ADDR_row, among the plurality of word lines.

The column decoder 160 may select any one among a plurality of bit lines coupled with the memory cell array 110. For example, the column decoder 160 may receive the column address ADDR_col from the control logic 120. The column decoder 160 may select any one bit line corresponding to the received column address ADDR_col, among the plurality of bit lines.

The first and second page buffers 170 and 180 may be coupled with the memory cell array 110 through the plurality of bit lines. The first page buffer 170 may temporarily store data including a command stored in the first command register 130. The second page buffer 180 may temporarily store data including a command stored in the second command register 140.

For example, if commands stored in the first and second command registers 130 and 140 are write commands, the first and second page buffers 170 and 180 may temporarily store write data provided from the memory controller 200 which are to be stored in the memory cell array. If commands stored in the first and second command registers 130 and 140 are read commands, the first and second page buffers 170 and 180 may temporarily store data read out from the memory cell array 110 corresponding to the read commands.

The command state register 190 may store at least one state information for the commands stored in the first and second command registers 130 and 140. A state information may include an execution result information indicating whether or not a command has been successfully executed. A state information may include an execution state information indicating whether execution of the command is completed, or is pending (hasn't started) or whether the command is in the process of being executed.

FIGS. 2A and 2B are diagrams illustrating representations of examples of the command state register 190.

Referring to FIG. 2A, the command state register 190 may include a plurality of fields (e.g., first to fourth fields F1 to F4). The first field F1 (“Pass/fail(n)” in FIG. 2A) may represent execution result information of an n{circumflex over ( )}th command, i.e. information indicating whether a command has been successfully executed (“Pass”) or has failed (“fail”). The second field F2 (“Pass/fail(n−1)” in FIG. 2A) may represent execution result information of an (n−1){circumflex over ( )}th command. The third field F3 (“Command state(n)” in FIG. 2A) may represent execution state information of the n{circumflex over ( )}th command such as, whether the command has been completed (“completion”), whether the command is pending (“pending”), and whether the command is currently in the process of being executed (“executing”). The fourth field F4 (“Command state(n−1)” in FIG. 2A) may represent execution state information of the (n−1){circumflex over ( )}th command. Here, ‘n’ may be an integer equal to or greater than 1. The (n−1){circumflex over ( )}th command may be a command which is transmitted earlier than the n{circumflex over ( )}th command from the memory controller 200. The arrangement sequence of the respective fields of the command state register 190 is not limited to the one shown in FIG. 2A, and may be changed according to design.

The respective execution state information of the third and fourth fields F3 and F4 may have 3 values (e.g., 0, 1 and 2) respectively indicating a corresponding command as execution-completed (“0: completion” in FIG. 2A), execution-pending (“1: pending” in FIG. 2A), and of in the process of being executed (“2: executing” in FIG. 2A). The execution-pending command may be stored in one of the first and second command registers 130 and 140, and may not be fetched yet. The on-the-execution command has been fetched and is in the process of being executed by the control logic 120. The on-the-execution command may be suspended by the control logic 120 while it is executed.

For example, as shown in FIG. 2A, if ‘1’ is stored in the third field F3 and ‘2’ is stored in the fourth field F4, the memory controller 200 determines, by checking the command state register 190, that the state of the (n−1){circumflex over ( )}th command is being executed and the state of the n{circumflex over ( )}th command is execution-pending. If ‘2’ is stored in both of the third and fourth fields F3 F4, the memory controller 200 determines that the (n−1){circumflex over ( )}th command is suspended during the execution and the n{circumflex over ( )}th command is currently executed. Generally, the memory device 100 may process only one command at any one time. Accordingly, the fact that two commands, i.e., both the (n−1){circumflex over ( )}th command and the n{circumflex over ( )}th command are being executed may mean that one command of the two commands was suspended during execution. At this time, since a command transmitted earlier is executed first, the memory controller 200 may determine that the (n−1){circumflex over ( )}th command is suspended and the n{circumflex over ( )}th command is currently executed.

The execution result information of the first and second fields F1 and F2 may have 2 values, e.g., 0 and 1 respectively indicating execution-pass and execution-fail (respectively “0: pass” and “1: fail” in FIG. 2A) of a corresponding command. The execution result information of a command may be updated by the control logic 120 after execution of the command is completed. For example, as shown in FIG. 2A, if ‘0’ is stored in the fourth field F4 and ‘0’ is stored in the second field F2, the memory controller 200 determines that the execution of the (n−1){circumflex over ( )}th command has been completed and the execution result of the (n−1){circumflex over ( )}th command is a pass, hence the memory controller 200 determines that the (n−1){circumflex over ( )}th command has been executed successfully

In the command state register 190 according to the present embodiment, values of the respective fields F1 to F4 may be updated each time the execution status of a corresponding command changes or each time the memory controller 200 provides a new command.

For example, if the (n−1){circumflex over ( )}th command is execution-completed, values of the second and fourth fields F2 and F4 for the execution-completed (n−1){circumflex over ( )}th command is erased from the command register 190, and the execution result information of the first field F1 and the execution state information of the fourth field F3 for the n{circumflex over ( )}th command may be respectively updated to be moved to the second field F2 and the fourth field F4, and the n{circumflex over ( )}th command is now regarded as the (n−1){circumflex over ( )}th command. If there is an (n+1){circumflex over ( )}th command transmitted from the memory controller 200, the execution result information and an execution state information on the (n+1){circumflex over ( )}th command may be stored in the first and third fields F1 and F3, respectively, and will be treated as the n{circumflex over ( )}th command.

If execution of the (n−1){circumflex over ( )}th command is completed, the (n−1){circumflex over ( )}th command is erased from a command register in which the (n−1){circumflex over ( )}th command is stored, and the corresponding command register may become an empty state.

The memory controller 200 may determine whether to transmit a command to the memory device 100, by checking the execution state informations of commands stored in the command state register 190. For example, the memory controller 200 may check the command state register 190, may determine, when execution of a certain command is completed, that one of two command registers, that is, the first command register 130 and the second command register 140, is empty, and may transmit a command to execute next, to the memory device 100. If it is determined that two commands correspond to executing or pending, the memory controller 200 may determine that no empty command register exists between the first command register 130 and the second command register 140, and may not transmit a command to execute next, to the memory device 100.

In another embodiment, referring to FIG. 2B, the command state register 190 may include first and second command state registers 190 a and 190 b. Each of the first and second command state registers 190 a and 190 b may include an execution result information field (“Pass/fail” in FIG. 2B) and an execution state information field (“Command state” in FIG. 2B) for a command. Also, each of the first and second command state registers 190 a and 190 b may include a tag information field (“Tag” in FIG. 2B). The execution result information and the execution state information of a command are described above with reference to FIG. 2A.

When the memory controller 200 transmits a command to the memory device 100, it may transmit together with the command a tag information. The tag information may indicate a command state register among a plurality of command state registers in which the state information relating to the received command is to be stored. Hence, when the memory device 100 stores state information for the received command, it stores the state information in the command state register which is designated by the tag information which was transmitted together with the command.

For example, as shown in the example of FIG. 2B, the tag information of the first command state register 190 a of the command state register 190 is set as ‘0’ and the tag information of the second command state register 190 b of the command state register 190 is set as ‘1.’ So for example, if the memory controller 200 transmits a command and a tag information of ‘0’ to the memory device 100, the memory device 100 may store state information for the command, in the first command state register 190 a for which the tag information is set as ‘0.’

If a state information request for the commands is received from the memory controller 200, the memory device 100 may transmit the state informations of the respective commands and tag informations corresponding to the respective commands to the memory controller 200. The memory controller 200 may check the tag informations, and determine execution states of the commands corresponding to the tag informations,

The control logic 120 may store a command transmitted from the memory controller 200, in the first command register 130 or the second command register 140. When transmitting a command to the memory device 100, the memory controller 200 may not designate whether the command is to be stored in the first command register 130 or the second command register 140.

The memory controller 200 checks the command state register 190, and transmits a command to the memory device 100 only when an empty command register exists, i.e., only when a command register having the execution state information field value of ‘0’ representing the execution-completion of a corresponding command.

The control logic 120 of the memory device 100 may store the command transmitted from the memory controller 200, in an empty command register between the first and second command registers 130 and 140.

FIGS. 3A to 3D illustrate the control logic 120 storing commands transmitted from the memory controller 200 into the command registers 130 and 140, and fetching the stored commands. For the sake of convenience in explanation, it is assumed that both the first and second command registers 130 and 140 are initially empty, i.e., there is initially no command that is execution-pending or in the process of being executed.

Referring to FIG. 3A, if a first command CMD1 is transmitted from the memory controller 200, the control logic 120 may store the transmitted first command CMD1 in the first command register 130. While it is illustrated in the present embodiment that the control logic 120 stores the first command CMD1 in the first command register 130, it is to be noted that this simply an example. For instance, alternatively, the control logic 120 may store the first command CMD1 in the second command register 140.

Referring to FIG. 3B, if, thereafter, a second command CMD2 is transmitted from the memory controller 200 while the first command CMD1 is execution-pending or in the process of being executed, the control logic 120 may store the transmitted second command CMD2 in the second command register 140 which is empty. In this way, if there is no empty command register as both of the first and second commands CMD1 and CMD2 of the first and second command registers 130 and 140 are execution-pending or in the process of being executed, the memory controller 200 may not transmit another command any more to the memory device 100, by checking the execution state information of the command register 190.

Also, as shown in FIG. 313, the control logic 120 may fetch the first command CMD1 from the first command register 130, and execute the fetched first command CMD1.

Referring to FIG. 3C, even though the first command CMD1 is fetched by the control logic 120, the first command CMD1 is still stored in the first command register 130. Namely, the first command register 130 may not be at an empty state until execution of the fetched first command CMD1 is completed. When execution of the fetched first command CMD1 is completed, then the first command register 130 transitions to an empty state. In this way, since the first command CMD1 is in the process of being executed and the second command CMD2 is execution-pending, the memory controller 200 does not transmit a new command to the memory device 100, by checking the execution state information of the command register 190.

When execution of the first command CMD1 is completed the first command register 130 transitions to an empty state, and then the memory controller 200 can transmit a third command CMD3 to the memory device 100. The control logic 120 then stores the transmitted third command CMD3 in the first command register 130 which is currently empty, as shown in FIG. 3D. The control logic 120 may then fetch the second command CMD2 from the second command register 140, and execute the fetched second command CMD2. When execution of the fetched second command CMD2 is completed, the control logic 120 may fetch the third command CMD3 from the first command register 130, and execute the fetched third command CMD3. Meanwhile, when at least one of the first and second command registers becomes empty then the memory controller 200 can transmit a new command to the memory device which can be stored in the at least one empty first or second command register.

Meanwhile, when the memory controller 200 transmits a write command to the memory device 100, it may also transmit write data together with the write command. The control logic 120 may store the write data in a page buffer corresponding to a command register in which the write command is stored. For example, in the case where the first command CMD1 is a write command, the control logic 120 may store the first command CMD1 in the first command register 130, and may store write data for the first command CMD1 in the first page buffer 170 corresponding to the first command register 130.

If a read command is transmitted from the memory controller 200, the control logic 120 in response to the transmitted read command may store data read out from the memory cell array 110 in a page buffer corresponding to a command register in which the read command is stored. For example, if the second command CMD2 transmitted from the memory controller 200 is a read command, the control logic 120 may store data, which is read out from the memory cell array 110 by execution of the second command CMD2, in the second page buffer 180 corresponding to the second command register 140.

If a newly transmitted command which is stored in the first or the second command register 130 or 140 has a higher priority than a command which is in the process of being executed, the control logic 120 may suspend the command which is in the process of being executed and execute the newly transmitted command that has higher priority. For example, the control logic 120 may determine whether or not the priority of a newly transmitted command from the memory controller 200 is higher than a command currently in the process of being executed. If the priority of the transmitted command is higher, the control logic 120 may then immediately suspend the command currently in the process of being executed, and execute the newly transmitted command having the higher priority. The control logic 120 may periodically check whether or not a command of a higher priority exists in the first and second command registers 130 and 140. If a command of a higher priority is detected, the control logic 120 may suspend a command in the process of being executed and having a lower priority and execute the command of the higher priority. If execution of the command of the higher priority is completed, the control logic 120 may then resume the execution of the suspended command.

In this way, since the memory device 100 may execute first a command of a higher priority by suspending a command currently in the process of being executed and having a lower priority and then resume the execution of the suspended command, the memory controller 200 does not need to transmit a separate suspend/resume command to the memory device 100.

Before suspending a command which is in the process of being executed, the control logic 120 may determine whether the suspend count of the command which is in the process of being executed exceeds a predetermined suspend count. The suspend count refers to the number of times the command has been suspended. Only when the suspend count is equal to or smaller than the predetermined suspend count, the control logic 120 may suspend the command in the process of being executed and execute first a command of a higher priority.

The control logic 120 may update state informations for the commands stored in the command state register 190. The control logic 120 may update execution state informations and execution result informations for commands stored in the first and second command registers 130 and 140, respectively.

The memory controller 200 may transmit to the memory device 100 a command, an address, control signals and so forth corresponding to a request from an external device. By referring to the command state register 190 of the memory device 100, if the execution state information represents a certain command as execution-completed, the memory controller 200 may determine that there is an empty command register, and transmit a new command to the memory device 100. Also, by referring to the command state register 190 of the memory device 100, if the execution state informations of all commands correspond to pending or executing, the memory controller 200 may determine that there is no empty command register, and not transmit a new command, to the memory device 100.

In accordance with an embodiment of the present disclosure, the memory device 100 includes a plurality of command registers (Le., the first and second command registers 130 and 140), and thus the memory controller 200 may transmit a new command to the memory device 100 when at least one of the plurality of the command registers have space for the new command even while the memory device 100 is busy in currently executing the command in a command register among the plurality of the command registers. In this way, since the memory device 100 may receive a new command even when it is in a busy state, a command reception interval may be shortened and thus the performance of the memory system 10 may be improved.

Moreover, since the memory device 100 may store plural commands, it may execute the stored plural commands without a halt, and thus the memory controller 200 may not need to transmit a separate cache command to the memory device 100 thereby reducing the number of commands and thus reducing the load of the interface between the controller and the memory devices or stated more simply simplifying the interface.

FIG. 4 is a block diagram illustrating a memory system 10 in accordance with another embodiment of the present invention.

Referring to FIG. 4, the memory system 10 of FIG. 4 may be the same as the memory system of FIGS. 1 to 4 except that unlike the embodiment of FIG. 1, the memory system of FIG. 4 includes a suspend condition register 195.

The suspend condition register 195 may store a setting information for a condition in which the memory device 100 performs a suspend operation. The register value of the suspend condition register 195 may be set by the memory controller 200. For example, the memory controller 200 may set the register value of the suspend condition register 195 when the memory device 100 is in a ready state. The control logic 120 of the memory device 100 may perform the suspend operation only under a corresponding condition, by referring to the register value set in the suspend condition register 195.

FIG. 5 is a diagram illustrating suspend condition register values and suspend conditions corresponding to the respective register values, in accordance with an embodiment of the present invention.

Referring to FIG. 5, the suspend condition register 195 may store one among a plurality of register values. While FIG. 5 illustrates register values from ‘0’ to ‘5’ and suspend conditions for the respective register values, it is to be noted that this is for an illustration purpose only and the embodiment is not specifically limited thereto.

For example, the memory controller 200 may set one of the values ‘0’ to ‘5’ as the register value of the suspend condition register 195. The control logic 120 may check the register value set in the suspend condition register 195, and perform a suspend operation under a corresponding suspend condition.

For example, referring to the example of FIG. 5, if the register value stored in the suspend condition register 195 is ‘0,’ the control logic 120 does not perform the suspend operation in any case. If the register value stored in the suspend condition register 195 is ‘1,’ the control logic 120 suspends erase execution and executes first a transmitted read command under a condition where the read command is transmitted during erase execution, and does not perform the suspend operation under the other conditions.

Similarly, if the register value stored in the suspend condition register 195 is ‘2/,’ the control logic 120 suspends erase execution and executes first a transmitted write command under a condition where the write command is transmitted during an erase execution, and does not perform the suspend operation under the other conditions. If the register value stored in the suspend condition register 195 is ‘3,’ the control logic 120 suspends erase execution and executes first a transmitted read command or write command under a condition where the read command or write command is transmitted during an erase execution, and does not perform the suspend operation under the other conditions.

If the register value stored in the suspend condition register 195 is ‘4,’ the control logic 120 suspends write execution and executes first a transmitted read command under a condition where the read command is transmitted during write execution, and does not perform the suspend operation under the other conditions. If the register value stored in the suspend condition register 195 is ‘5,’ the control logic 120 suspends write or erase execution and executes first a transmitted read command under a condition where the read command is transmitted during a write or an erase execution, and does not perform the suspend operation under the other conditions.

In other words, the control logic 120 of the memory device 100 may perform the suspend operation only under a corresponding condition by referring to a suspend condition register value set in advance by the memory controller 200.

FIG. 6 is a flow chart of a method for operating the memory system 10, according to an embodiment of the present invention. FIG. 1.

At step S610, the memory controller 200 may check whether the execution-completed command is included in the first and second command registers 130 and 140 by referring to the command state register 190.

If execution of at least one of the commands stored in the first and second command registers 130 and 140 is completed, then at least one of the first and second command registers 130 and 140 of the execution-completed command becomes empty.

At step S620, the memory controller 200 may determine whether at least one of the first and second command registers 130 and 140 is empty (i.e., a corresponding command is execution-completed) based in the process of being executed state informations of the commands stored in the command state register 190.

Steps S610 and S620 may be repeated until at least one of the first and second command registers 130 and 140 is determined as empty (i.e., a corresponding command is execution-completed).

When at least one of the first and second command registers 130 and 140 is determined as empty (i.e., a corresponding command is execution-completed) at step S620, the memory controller 200 may transmit a new command to the memory device 100 at step S630.

At step S640, the memory device 100 may store the command transmitted from the memory controller 200 in the empty command register. In the case where both the first and second command registers 130 and 140 are determined as empty, the memory device 100 may store the transmitted command in either one of the first and second command registers 130 and 140.

FIG. 7 is a flow chart of a method for performing the suspend operation of the memory device 100 according to an embodiment of the present invention. For the sake of convenience in explanation, a command having a lower priority will be referred to as a low command and a command having a higher priority will be referred to as a high command. It is assumed that a low command is stored in the first command register 130 of the memory device 100.

At step S710, the control logic 120 of the memory device 100 may fetch the low command from the first command register 130, and execute the fetched low command.

At step S720, if a new command is transmitted from the memory controller 200, the control logic 120 may store the transmitted command in the second command register 140, and may determine whether the transmitted command is a high command.

When the transmitted command is determined as a high command, the control logic 120 may determine whether the suspend count of the low command currently in the process of being executed exceeds a predetermined suspend count PSC at step S730. When the suspend count of the low command currently in the process of being executed is determined as equal to or smaller than the predetermined suspend count, the control logic 120 may suspend operation to the low command currently in the process of being executed at step S740. At this time, the control logic 120 may back up a register value necessary for execution of the low command and data.

At step S750, the control logic 120 may fetch the high command from the second command register 140, and execute the fetched high command.

At step S760, the control logic 120 may determine whether execution of the high command is completed. As a result of determination, if execution of the high command is completed, step S770 may be performed.

At the step S770, the control logic 120 may resume execution of the low command currently suspended, and the control logic 120 may complete execution of the low command at the step S780.

When the transmitted command is not determined as a high command at step S720 or the suspend count of the low command currently in the process of being executed is not determined as equal to or smaller than the predetermined suspend count at step S730, the control logic 120 may complete execution of the low command at the step S780.

FIG. 8 is a flow chart of a method for performing the suspend operation of the memory device 100 according to an embodiment of the present invention. It is assumed that a low command is stored in the first command register 130 of the memory device 100.

At step S810, the control logic 120 of the memory device 100 may fetch the low command from the first command register 130, and execute the fetched low command.

At step S820, the control logic 120 may check the other command register, i.e., the second command register 140.

At step S830, the control logic 120 may determine whether a high command is stored in the second command register 140.

When the second command register 140 is determined to store the high command at step S830, the control logic 120 may determine whether the suspend count of the low command currently in the process of being executed exceeds a predetermined suspend count PSC at step S840.

When the suspend count of the low command currently in the process of being executed is determined as equal to or smaller than the predetermined suspend count PSC, the control logic 120 may suspend operation to the low command currently in the process of being executed. At this time, the control logic 120 may back up a register value necessary for execution of the low command and data.

At step S860, the control logic 120 may fetch the high command from the second command register 140, and execute the fetched high command.

At step S870, the control logic 120 may determine whether execution of the high command is completed. As a result of the determination, if execution of the high command is completed, step S880 may be performed.

At the step S880, the control logic 120 may resume execution of the low command currently suspended, and the control logic 120 may complete execution of the low command at the step S890.

When the second command register 140 is determined not to store the high command at step S830 or the suspend count of the low command currently in the process of being executed is not determined as equal to or smaller than the predetermined suspend count PSC at step S840, the control logic 120 may complete execution of the low command at the step S890.

FIG. 9 is a block diagram illustrating a data processing system 1000 including a memory system 1200, in accordance with an embodiment of the present invention.

Referring to FIG. 9, the data processing system 1000 may also include a host device 1100 operatively coupled to the memory system 1200.

The memory system 1200 may include a controller 1210 and a nonvolatile memory device 1220. The memory system 1200 may be used by being coupled to the host device 1100 such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game player, a TV, an in-vehicle infotainment system, and so forth.

The nonvolatile memory device 1220 may configured according to the memory device of FIG. 1 or 4 and may include two command registers (see FIG. 1) which store commands transmitted from the controller 1210, and a command state register (see FIG. 1) which stores respective state informations of the commands stored in the respective command registers.

The controller 1210 may include a host interface unit 1211, a control unit 1212, a memory interface unit 1213, a random access memory 1214, and an error correction code (ECC) unit 1215.

The random access memory 1214 may be used as the working memory of the control unit 1212. The random access memory 1214 may be used as a buffer memory which temporarily stores data read out from the nonvolatile memory device 1220 or data provided from the host device 1100.

The control unit 1212 may control one or more operations of the controller 1210 in response to a request from the host device 1100. The control unit 1212 may drive a firmware or a software for controlling the nonvolatile memory device 1220.

The control unit 1212 may determine whether an empty command register exists between the two command registers, by checking the command state register of the nonvolatile memory device 1220, may transmit a command to execute next, to the nonvolatile memory device 1220 when an empty command register exists, and may not transmit a command to the nonvolatile memory device 1220 when an empty command register does not exist.

The host interface unit 1211 may interface the host device 1100 and the controller 1210. For example, the host interface unit 1211 may communicate with the host device 1100 through one of various interface protocols such as a universal serial bus (USB) protocol, a universal flash storage (UFS) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI express (PCI-E) protocol, a parallel advanced technology attachment (PATH) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, and a serial attached SCSI (SAS) protocol.

The memory interface unit 1213 may interface the controller 1210 and the nonvolatile memory device 1220. The memory interface unit 1213 may provide a command and an address to the nonvolatile memory device 1220. Furthermore, the memory interface unit 1213 may exchange data with the nonvolatile memory device 1220.

The error correction code (ECC) unit 1215 may ECC-encode data to be stored in the nonvolatile memory device 1220. Also, the error correction code (ECC) unit 1215 may ECC-decode data read out from the nonvolatile memory device 1220. Moreover, the error correction code (ECC) unit 1215 may count the number of error bits corrected in the process of ECC-decoding data, and calculate the total number of corrected error bits. The error correction code (ECC) unit 1215 may be included in the memory interface unit 1213.

The controller 1210 and the nonvolatile memory device 1220 may be manufactured as any one of various data storage devices. For example, the controller 1210 and the nonvolatile memory device 1220 may be integrated into one semiconductor device and may be manufactured as any one of a multimedia card in the form of an MMC, an eMMC, an RS-MMC and a micro-MMC, a secure digital card in the form of an SD, a mini-SD and an micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card, a compact flash (CF) card, a smart media card, a memory stick, and so forth.

FIG. 10 is a block diagram illustrating a data processing system 2000 including a solid state drive (SSD) 2200 in accordance with an embodiment of the present invention.

Referring to FIG. 10, the data processing system 2000 may also include a host device 2100 operatively coupled to the solid state drive (SSD) 2200.

The SSD 2200 may include an SSD controller 2210, a buffer memory device 2220, nonvolatile memory devices 2231 to 223 n, a power supply 2240, a signal connector 2250, and a power connector 2260.

The SSD controller 2210 may access the nonvolatile memory devices 2231 to 223 n in response to a request from the host device 2100.

The buffer memory device 2220 may temporarily store data to be stored in the nonvolatile memory devices 2231 to 223 n. Further, the buffer memory device 2220 may temporarily store data read out from the nonvolatile memory devices 2231 to 223 n. The data temporarily stored in the buffer memory device 2220 may be transmitted to the host device 2100 or the nonvolatile memory devices 2231 to 223 n under control of the SSD controller 2210.

The nonvolatile memory devices 2231 to 223 n may be used as storage media of the SSD 2200. The nonvolatile memory devices 2231 to 223 n may be coupled with the SSD controller 2210 through a plurality of channels CH1 to CHn, respectively. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to each channel may be coupled to the same signal bus and data bus.

Each of the nonvolatile memory devices 2231 to 223 n may be configured according to the memory device of FIG. 1 or 4 and may include two command registers (see FIG. 1) which store commands transmitted from the SSD controller 2210, and a command state register (see FIG. 1) which stores respective state informations of the commands stored in the respective command registers.

The power supply 2240 may provide power PWR inputted through the power connector 2260, to the inside of the SSD 2200. The power supply 2240 may include an auxiliary power supply 2241. The auxiliary power supply 2241 may supply power to allow the SSD 2200 to be normally terminated when a sudden power-off occurs. The auxiliary power supply 2241 may include large capacitance capacitors capable of charging power PWR.

The SSD controller 2210 may exchange a signal SGL with the host device 2100 through the signal connector 2250. The signal SGL may include a command, an address, data, and so forth. The signal connector 2250 may be configured by a connector such as of parallel advanced technology attachment (DATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI) and PCI express (PCI-E) protocols, according to an interface scheme between the host device 2100 and the SSD 2200.

FIG. 11 is a block diagram illustrating the SSD controller of FIG. 10.

Referring to FIG. 11, the SSD controller 2210 may include a memory interface unit 2211, a host interface unit 2212, an error correction code (ECC) unit 2213, a control unit 2214, and a random access memory 2215 operatively coupled via at least one internal bus.

The memory interface unit 2211 may provide control signals such as commands and addresses to the nonvolatile memory devices 2231 to 223 n. Moreover, the memory interface unit 2211 may exchange data with the nonvolatile memory devices 2231 to 223 n. The memory interface unit 2211 may scatter data transferred from the buffer memory device 2220 to the respective channels CH1 to CHn, under control of the control unit 2214. Furthermore, the memory interface unit 2211 may transfer data read out from the nonvolatile memory devices 2231 to 223 n to the buffer memory device 2220, under control of the control unit 2214.

The host interface unit 2212 may provide interfacing with respect to the SSD 2200 in correspondence to the protocol of the host device 2100. For example, the host interface unit 2212 may communicate with the host device 2100 through any one of the parallel advanced technology attachment (PATA) protocol, the serial advanced technology attachment (SATA) protocol, the small computer system interface (SCSI) protocol, the serial attached SCSI (SAS) protocol, the peripheral component interconnection (PCI) protocol and the PCI express (PCI-E) protocol.

In addition, the host interface unit 2212 may perform a disk emulating function of supporting the host device 2100 to recognize the SSD 2200 as a hard disk drive (HDD).

The control unit 2214 may analyze and process the signal SGL inputted from the host device 2100. The control unit 2214 may control operations of the buffer memory device 2220 and the nonvolatile memory devices 2231 to 223 n according to a firmware or a software for driving the SSD 2200.

The random access memory 2215 may be used as the working memory of the control unit 2214.

The control unit 2214 may analyze and process the signal SGL inputted from the host device 2100. The control unit 2214 may control operations of the buffer memory device 2220 and the nonvolatile memory devices 2231 to 223 n according to a firmware or a software for driving the SSD 2200.

The control unit 2214 may determine whether an empty command register exists, by checking the command state register of each of the nonvolatile memory devices 2231 to 223 n, may transmit a command to execute next, to each of the nonvolatile memory devices 2231 to 223 n when an empty command register exists, and may not transmit a command to each of the nonvolatile memory devices 2231 to 223 n when an empty command register does not exist.

The error correction code (ECC) unit 2213 may generate parity data to be transmitted to the nonvolatile memory devices 2231 to 223 n, among data stored in the buffer memory device 2220. The generated parity data may be stored, along with data, in the nonvolatile memory devices 2231 to 223 n. The error correction code (ECC) unit 2231 may detect an error of the data read out from the nonvolatile memory devices 2231 to 223 n. When the detected error is within a correction capability range, the error correction code (ECC) unit 2213 may correct the detected error. Moreover, the error correction code (ECC) unit 2213 may count the number of corrected error bits, and calculate the total number of corrected error bits.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the memory system and the operating method thereof described herein should not be limited based on the described embodiments. Many other embodiments and variations thereof may be envisaged by those skilled in the art to which the present invention pertains without departing from the scope and spirit of the present invention as defined in the following claims. 

What is claimed is:
 1. A memory system comprising: a memory device configured to include a plurality of command registers and a command state register storing execution state information of a plurality of commands stored in the plurality of the command registers; and a memory controller configured to determine whether an empty command register exists among the plurality of command registers based on the execution state information stored in the command state register, and transmit a new command to the memory device, when the empty command register exists.
 2. The memory system according to claim 1, wherein, when the new command is received from the memory controller, the memory device stores the new command in the empty command register.
 3. The memory system according to claim 1, wherein the execution state information represents that the command of the respective command registers is execution-pending, currently being executed, or execution-completed.
 4. The memory system according to claim 3, wherein, when the execution state information of a command stored in at least one of the plurality of the command registers represents the execution-completed, the memory controller determines at least one of the plurality of the command registers is the empty command register.
 5. The memory system according to claim 3, wherein the execution state information of the command stored in the respective command registers is updated according to current execution status of the command, and wherein when the command becomes execution-completed, a corresponding one storing the execution-completed command among the command registers becomes empty.
 6. A method for operating a memory system including a memory device, which includes a plurality of command registers and a command state register storing execution state information of a plurality of commands stored in the plurality of the command registers, and a memory controller, the method comprising: determining, by the memory controller, whether an empty command register exists among the plurality of command registers based on the execution state information stored in the command state register; and transmitting, by the memory controller, a new command to the memory device when the empty command register exists.
 7. The method of claim 6, further comprising: storing, by the memory device, the new command received from the memory controller in the empty command register.
 8. The method of claim 6, wherein the determining of whether the empty command register exists includes: checking the execution state information of each of the plurality of the commands stored in the plurality of the command registers; and determining whether at least one of the plurality of the commands is execution-completed.
 9. The method of claim 6, further comprising: updating, by the memory device, the execution state information of the command stored in the respective command registers is updated according to current execution status of the command.
 10. The method of claim 6, wherein the plurality of the commands stored in the plurality of the command registers are executed in order of priority.
 11. A memory system comprising: a memory device including a plurality of command registers for storing provided commands, and suitable for executing the stored commands; and a memory controller suitable for controlling the memory device by providing the commands to the memory device, wherein a memory controller provides a new command to the memory device when one or more among the stored commands are execution-completed, and wherein the memory device stores the new command in one among the command registers corresponding to the execution-completed commands.
 12. The memory system of claim 11, wherein the memory device further includes a command state register for storing execution statuses of the stored commands, and wherein the memory device updates the execution statuses at least when one or more of the stored commands are execution-completed.
 13. The memory system of claim 12, wherein the memory controller determine whether to provide the new command according to the execution statuses.
 14. The memory system of claim 13, wherein the memory device executes the stored command in order of priority.
 15. The memory system of claim 14, wherein the memory device suspends a command in the process of being executed and having a lower priority, and executes another command having a higher priority, among the stored commands.
 16. A method for operating a memory system including a memory device and a memory controller, the method comprising: providing, by the memory controller, commands to the memory device; storing, by the memory device, the provided commands in command registers of the memory device; and executing, by the memory device, the stored commands, wherein a new command is provided to the memory device when one or more among the stored commands are execution-completed, and wherein the new command is stored in one among the command registers corresponding to the execution-completed commands.
 17. The method of claim 16, further comprising: storing execution statuses of the stored commands; and updating the execution statuses at least when one or more of the stored commands are execution-completed.
 18. The method of claim 17, wherein the providing of the commands includes determining, by the memory controller, whether to provide the new command according to the execution statuses.
 19. The method of claim 18, wherein the stored commands are executed in order of priority.
 20. The method of claim 19, wherein the executing of the stored commands includes: suspending, by the memory device, a command in the process of being executed and having a lower priority among the stored commands, and executing, by the memory device, another command having a higher priority among the stored commands. 